1. Field of the Invention
The present invention relates to a process of producing a semiconductor device; and more particularly, to a dry etching technique for patterning small geometries.
2. Discussion of the Related Art
Etching techniques in conjunction with lithography are important for producing denser and smaller semiconductor devices. Dry etching techniques have been developed for the manufacture of semiconductor devices having reduced dimensions. FIGS. 9-12 show a known method of producing CMOS-FETs with dry etching. This method will be described below.
FIG. 9 illustrates a p.sup.+ -type (high impurity concentration p-type) silicon wafer 21 and a p.sup.- -type (low impurity concentration p-type) epitaxial layer 22 formed thereon. Photoresist layer 23 is disposed on p.sup.- -type epitaxial layer 22. Window openings 24' are provided in photoresist layer 23 for forming trench grooves that will facilitate element separation isolation.
Photoresist layer 23 serves as a mask layer, such that exposed portions of p.sup.- -type epitaxial layer 22 in window openings 24' are plasma etched. As a result, trench grooves 24 are formed in p.sup.- -type epitaxial layer 22 as shown in FIG. 10. Boron ions are injected onto the bottoms of the trench grooves 24 to form channel stop or channel cut layer 25 (shown in FIG. 11).
As further seen in FIG. 11, sidewall insulating film 26 is then formed on the inner sidewall of each trench groove 24 after channel stop layer 25 has been formed. Trench grooves 24 are also filled with polycrystalline silicon 27. Subsequently, photoresist layer 23a is disposed on p.sup.- -type epitaxial layer 22. Photoresist layer 23 is patterned to form window openings 28'. Phosphorus ions are injected (i.e., implanted) into window openings 28' to form n-type well regions 28 (FIG. 12) in which p-channel MOS transistors will be formed.
After n-wells 28 are formed by ion implantation as shown in FIG. 12, p.sup.+ -type source and drain regions 29a and 30a are formed in each n-well 28. On the other hand, n.sup.+ -type source and drain regions 29b and 30b of n-channel transistor 35b are formed in p.sup.- -type epitaxial layer 22. In addition, gate oxide films 31a and 31b, gate electrodes 32a and 32b, and layer-to-layer insulating films 33a, 33b and 33c are formed on the surface of p.sup.- -type epitaxial layer 22. Then aluminum electrodes 34a, 34b, 34c, 34d, 34e and 34f are connected to the source, gate and drain of the p-channel transistors and the drain, gate and source of the n-channel transistors, respectively. As a result, p-channel MOS transistors 35a and n-channel MOS transistors 35b are formed having appropriate electrical connections.
A number of semiconductor devices 35 each having p-channel MOS transistors 35a and n-channel MOS transistor 35b are formed on p.sup.+ -type silicon wafer 21. Semiconductor devices 35 are isolated from one another via a scribe line zones 36 which are used for cleaving (cutting and dividing) p.sup.+ -type silicon wafer 21.
However, the areas subjected to plasma etching correspond only to window openings 24' where trench grooves 24 are formed. These areas account for a very small percentage of the total surface area on one side of the p.sup.+ -type silicon wafer. If plasma etching is performed in an atmosphere containing chlorine or fluorine, the ratio of the etched area to the concentration of ions or radicals (used as etching species) will tend to be very low. Consequently, the directional selectivity of the etching will be reduced.
As a result, the etched area must be increased, thereby increasing the area separating the p-channel MOS transistor 35a from n-channel MOS transistor 35b. The area between the n- and p-channel MOS transistors is further increased because etching also extends in the direction of the sidewall of trench groove 24 (i.e., side etching) occurs. Accordingly, it has become difficult to increase device density when a dry etching process is used.